Senior Principal PCIE PHY Signal & Power Integrity Engineer

Architect the Electrical Foundations of AI, Cloud, and Next-Generation Connectivity

At MaxLinear, we're developing breakthrough semiconductor solutions that power the world's fastest networks, AI infrastructure, cloud data centers, and advanced communication systems. We're seeking a Senior Principal PCIe PHY Validation Engineer to lead hands-on electrical validation, compliance readiness, and system-level debug for high-speed PCIe interfaces used in cutting-edge hardware platforms optimized for high-performance storage accelerator solutions.  

The ideal candidate has deep PCIe PHY bring-up and characterization experience, strong lab discipline, and the ability to connect measurements, link behavior, compliance results, firmware settings, and system architecture into clear engineering decisions. This role demands deep expertise in PCIe Gen5/Gen6 protocols, hands-on debugging, and board-level design of PCIe, OCP, and EDSFF form factors. You will drive architecture, design, validation, compliance with industry standards, and support of at-scale manufacturing.

Your Mission

You will serve as the subject matter expert on PCIe Gen5 and Gen 6 protocols and physical layer implementation. You will own the validation strategy and technical execution for PCIe PHY interfaces from pre-silicon planning through silicon bring-up, board-level validation, compliance preparation, interoperability debug, and production readiness. You will partner with silicon design, firmware, systems, board design, SI/PI, manufacturing, and customer-facing teams to ensure our PCIe implementations meet performance, robustness, and compliance expectations across real platforms.

What You'll Do

Own PCIe PHY validation strategy

Define validation plans for PCIe PHY electrical characterization, compliance readiness, interoperability, margining, and stress testing across silicon and board revisions.

Translate PCIe Base/CEM requirements and platform use cases into executable lab tests, clear pass/fail criteria, and risk-based validation coverage including DVT and PVT phases.

Lead hands-on electrical characterization

Characterize transmitter, receiver, reference clock, reset, link equalization, lane margining, and high-speed channel behavior using high-bandwidth oscilloscopes, BERTs, pattern generators, protocol analyzers, and compliance test tools. Analyze eye diagrams, jitter, equalization behavior, presets, CTLE/DFE settings, SSC impact, de-emphasis, insertion loss, return loss, crosstalk, and channel margin under realistic system conditions.

Lead Advanced Modeling and Simulation

Utilize state-of-the-art simulation platforms to predict, analyze, and optimize system performance before hardware is built, ensuring first-pass success and accelerated product development. Architect and implement high-speed interface designs, including PCIe Gen5/6 and OCP-compliant protocols for PCIe HHHL, OCP 3.0 NIC, and EDSFF form factor boards for high-volume production.

Drive PCIe bring-up and debug

Debug link training and stability issues using LTSSM analysis, firmware logs, register dumps, protocol traces, electrical captures, and controlled experiments.

Isolate PHY, board, package, connector, retimer/redriver, reference clock, reset, power, firmware, BIOS, and host-platform contributors to failure signatures.

Prepare products for compliance and interoperability

Plan and execute PCIe compliance-oriented testing, including transmitter/receiver characterization, stressed conditions, interoperability runs, and failure reproduction ahead of external compliance events.

 
Work with internal and external labs, ecosystem partners, and platform teams to close compliance gaps with data-driven recommendations.

Support manufacturing and customers

Support Functional Circuit Test (FCT) and In-Circuit Test (ICT) processes. Support key customers through product ramps. Lead RMA analysis and work closely with customers and manufacturing teams to resolve board-level issues.

Be the technical authority for PCIe PHY validation

Mentor engineers, review validation plans and results, lead difficult technical investigations, communicate risks, tradeoffs, and recommendations to engineering leadership

What Makes You Exceptional

You are passionate about solving complex electrical challenges that others consider impossible. You combine deep theoretical knowledge with practical engineering intuition and thrive in environments where innovation, collaboration, and technical excellence matter.  

You'll Bring

• Extensive hands-on experience validating PCIe PHYs or high-speed SerDes interfaces at silicon, board, or system level.
• Practical lab expertise with high-bandwidth oscilloscopes, BERTs, protocol analyzers, compliance software, pattern generators, VNAs/TDRs, differential probes, and precision clock/jitter measurement equipment.
• Experience with PCIe electrical concepts such as eye margin, jitter decomposition, transmitter presets, receiver equalization, CTLE, DFE, de-emphasis, SSC, reference clock quality, channel loss, crosstalk, and compliance masks.
• Ability to debug complex interactions across PHY settings, firmware, BIOS, host platforms, add-in cards, retimers/redrivers, connectors, cables, board layout, power delivery, and thermal conditions.
• Strong data analysis and automation skills using Python, lab instrument APIs, register access scripts, log parsing, and structured result reporting.
• Proven ability to lead cross-functional engineering debug, make technically grounded recommendations, and communicate clearly with design, firmware, systems, SI/PI, manufacturing, and leadership teams.

Preferred Experience

• Working knowledge of high-speed channel modeling, S-parameters, insertion/return loss, package/board effects, and correlation between simulation and measurement.
• Experience with Linux-based bring-up, low-level register debug, firmware-controlled PHY tuning, diagnostic utilities, and production validation flows.
• Background in SI/PI to close the loop between measured PHY behavior, channel design, and board/package implementation.
• PCB and package layout expertise using Cadence Allegro, APD, or similar tools.
• Familiarity with IC floor planning, EM/IR analysis, and advanced silicon-package-system co-design methodologies.

Why Join MaxLinear?

At MaxLinear, you'll work on technologies that enable the next generation of AI, cloud computing, wireless connectivity, and high-speed networking. You'll tackle problems that push the limits of physics, collaborate with some of the industry's most innovative engineers, and play a key role in delivering products that impact millions of users worldwide.

MaxLinear is a global, NASDAQ-traded company (MXL) where the entrepreneurial spirit is alive and well. We are a fabless system-on-chip product company, striving to improve the world’s communication networks for everyone through our highly integrated radio-frequency (RF), analog, digital, and mixed-signal semiconductor solutions for access and connectivity, wired and wireless infrastructure, and industrial and multi-market applications.

We hire the best people in the industry and engage them in some of the most exciting opportunities that connect the world we live in today. Our growth has come from innovative, bold approaches to solving some of the world’s most challenging communication technology problems in the most efficient and effective manner.

MaxLinear began by developing the world’s first high-performance TV tuner chip using standard CMOS process technology. Others said we couldn’t achieve the extremely high-performance requirements using CMOS, but we proved them wrong and achieved enduring global market leadership with our designs. Since then, we’ve developed a full line of products that drive 4G and 5G infrastructure; enable data center, metro and long-haul optical interconnects; bring 10Gbit to the home; power the IoT revolution; and enable robust and reliable communication in harsh industrial environments. Over the years, we’ve expanded through organic growth and through several acquisitions that have perfectly complemented our existing portfolio and enabled us to deliver complete end-to-end solutions in our target markets. One such example was the acquisition of Intel’s Home Gateway Platform Division that added Wi-Fi, Ethernet, and Broadband Gateway Processor SoC technology to our connected home portfolio creating a complete and scalable platform of connectivity and access solutions to fully address our customers’ needs.

Our headquarters are in Carlsbad, near San Diego, California. We also have major design centers in Irvine and San Jose, California; Valencia, Spain; Bangalore, India; Munich, Germany; Israel; and Singapore.

We have approximately 1,200 employees, a substantial majority of whom have engineering degrees and include masters and Ph.D. graduates from many of the premiere universities around the world. Our employees thrive on innovation, outstanding execution, outside-the-box thinking, nimbleness, and collaboration. Together, we form a high-energy business team that is focused on building the best and most innovative products on the market.