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Location : Location ES-Paterna
MaxLinear is searching for a Staff Software Test Engineer to join our Valencia design center. Join a motivated multidisciplinary team running state-of-the-art validation processes for embedded systems, passionate for automation, efficiency and continuous improvement, where Validation/Test Engineers provide high value to the product development and delivery chains, and take advantage of a very competitive salary, bonus and stock options program among other benefits.   You will work in an experienced team whose main goal is to ensure quality, performance and reliability of Embedded Software and Communications Systems supplied to customer. - Review and learn from system specifications designed by development teams. - Design test suites to measure product/system requirements quality indicators. - Automate test suites at system level with scripting languages and lab instrumentation APIs. - Participate in the maintenance and growth of existing Cloud-based test infrastructure. - Execute, analyze and report results of Software and System Test Plans. - Report and track defects, and verify associated fixes. - Make the team grow by contributing to methods and procedures that boost efficiency. - Develop new tools and scripts to improve daily validation teams tasks and test plan.
Category
PECS Engg
ID
2021-1688
Location : Location ES-Paterna
We are a team of world-class communication systems engineers designing advanced broadband communication SOCs.  These chips integrate complete PHY and MAC layers (including broadband RF/analog circuits, digital ASIC, and CPU subsystems) on a single die, and are being designed in deep-submicron CMOS processes for use in next-generation wireless, optical, and wireline systems.   MaxLinear is seeking a Senior Staff Communications Systems Engineer to join our experienced team in Valencia design center. Your responsibilities will include: - Design, verification and test of Medium Access Control (MAC), resource allocation and network control mechanisms and algorithms for broadband communication SOCs. - Performance evaluation and optimization of MAC and resource allocation algorithms at network level by modelling them using Network Simulation tools (i.e NS-3). Matching and aligning the models to the real HW/SW implementation. - Definition, specification and test of the HW/SW partitioning of the MAC and Data Path blocks and subsystems designed  to meet specific requirements. Collaboration with the ASIC Design and Firmware engineering teams to ensure the correct implementation
Category
Communications Systems Engineering
ID
2021-1460
Location : Location ES-Paterna
MaxLinear is seeking a Verification Engineer to join the ASIC team in Valencia design center. In this role, will work on the verification for digital SoC and signal processing chipsets with integrated analog components and high-speed networking interfaces. - Experience in verification strategy development and execution for large SoCs and signoff with coverage metrics - Knowledge of UVM methodology, SystemC and System Verilog - Implementation of randomized and directed random testbenches for networking and multi-cpu environments - Experience with gate level simulations of delay annotated netlists - Knowledge of verification IP and functional coverage techniques - Experience with signoff of SoC designs with coverage metrics - Experience with design would be a plus
Category
ASIC Engineering
ID
2021-1454
Location : Location ES-Paterna
Maxlinear is seeking a DFT Design engineer and contribute to large SOC implementation for advanced Communication ICs.  In this role, you will focus on: - Responsible for functional analysis for DFT (Design For Test). Using Scan, Memory BIST, Memory reparation, Boundary Scan, Functional BIST and e-fuses - Work on Digital DFT architecture, doing RTL design for DFT, DFT verification, ATPG and support for DFT test patterns bring-up. - Develop RTL for auxiliary blocks that impact on DFT architecture - Responsible for all aspects of physical implementation, include floor-planning, physical synthesis, clock-tree synthesis, parasitic extraction, physical verification and chip closure - Work closely with physical design team and design teams throughout the IC development
Category
ASIC Engineering
ID
2021-1448
Location : Location ES-Paterna
Maxlinear is seeking a Principal SoC Physical Design Engineer and be part of a SoC LPS team dealing with complex Communication ICs (wifi, router, PHY) in 16nm/7nm/5nm. In this role, you will focus on: - Responsible for toplevel and blocks whose complexity is at the limit of current tool capacity - To contribute in most aspects of physical implementation, including floor-planning, physical synthesis, clock-tree synthesis, parasitic extraction, physical verification and chip closure - Responsible for IO ring design and bump implementation, meeting ESD, EMI and SSO requirements - Implementation of Low power layout methodology (multiple switchable power domains, level shifter) - Execution of static and dynamic drop, ramp up analysis using Redhawk - Perform static timing analysis to handle complex timing closure. - Work with other design engineer in Synthesis, Design for Testability, STA/timing closure and Equivalent checks to resolve issues.  
Category
ASIC Engineering
ID
2021-1447
Location : Location ES-Paterna
Maxlinear is seeking a SoC Physical Design Manager to create and lead a Physical Design team dealing with complex Communication ICs (wifi, router, PHY) in 16nm/7nm/5nm. In this role, you will focus on: - Manage the Physical Design team in Valencia site, to perform a true RTL to GDSII flow. - Work with other sites on deploying the design flows for new technologies - Manage the local Physical design team toward excellence and project objectives - Responsible for toplevel and blocks whose complexity is at the limit of current tool capacity - Responsible for all aspects of physical implementation, include floor-planning, physical synthesis, clock-tree synthesis, parasitic extraction, physical verification and chip closure - Responsible for IO ring design and bump implementation, meeting ESD, EMI and SSO requirements - Implementation of Low power layout methodology (multiple switchable power domains, level shifter) - Perform static timing analysis to handle complex timing closure. - Work with other design engineer in Synthesis, Design for Testability, STA/timing closure and Equivalent checks to resolve issues.  
Category
ASIC Engineering
ID
2021-1446
Location : Location ES-Paterna
MaxLinear is seeking a Systems Applications Engineer to join our Valencia design center team. In this role, you will use your technical expertise, interpersonal and communication skills while focusing on the following: - Work with regional Sales and FAE teams to secure design wins and strengthen relationships with key customers and strategic partners: - Communicate and clarify customer system specifications and application requirements. - Demonstrate MaxLinear product evaluations and present technical seminars at customer sites and trade show events - Support and track customer design, bring-up, validation, and debug activities - Provide product and technical trainings for regional Sales and FAE teams - Work with internal teams: - Reproduce customer issues and finish primary debug - Clarify customer reported issues and provide correct information to internal team - Support regression and stress testing - Gather information from customers and the market to support marketing: - Perform feasibility studies on new product features - Support marketing team to define new products and roadmap - Conduct competitive intelligence studies and analyses - Support MaxLinear product development: - Develop product test plans and generate test reports - Generate product collateral and customer support documents including application notes, datasheets, and users’ guides - Conduct field test and analysis for new products - Work with the Engineering teams to improve product reliability, quality, and product experience - Support MaxLinear lab team: - Manage, Test and delivery EVKs to FAEs or customers
Category
Field Applications Engineering
ID
2021-1437
Location : Location ES-Paterna
MaxLinear is seeking an experienced DevOps Engineer to join the Software QA team in our Valencia design center. We are searching an excellent professional to add new features and conduct infrastructure architecture, scalability, and reliability to support Python-based test frameworks, test automation and quality measurement for our innovative embedded software and systems. Option to be full Work From Home.   In this role, you will focus on the following areas:   - Work closely with other DevOps teams to integrate and support test frameworks into CI/CD flow - Provide infrastructure solutions to meet QA team workflows - Provide solutions to scale infrastructure to support multiple software configurations - Learn how infrastructure is deployed and implement new deployment features - Support CI/CD needs for existing infrastructure - Define new workflows to boost team processes efficiency in the usage of the test framework - Collaborate with Automation Engineers to agree on infrastructure support and test repositories management - Collaborate with QA Engineers to include project KPI metrics and test artifacts management in the test framework - Support other non-SW project teams to provide solutions for project-specific needs in the infrastructure side  
Category
Software Engineering
ID
2021-1315
Location : Location ES-Paterna
MaxLinear is searching for a Staff Software Development Engineer to join our Valencia design center. For this role, we are open to new grads and senior engineers. The candidate will be integrated in a dynamic cross functional team to develop cutting-edge communication systems. The main activities will be: - Development of real-time firmware for embedded systems. - Specification and implementation of drivers, algorithms and protocols to be integrated in our communications systems, such as WiFi, MOCA, G.hn and Docsis. - Responsible for low-level design, implementation and unit testing of key features in networking technologies. - Participation in continuous improvement.
Category
Software Engineering
ID
2021-1305